1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and an amplification solid state image pick-up apparatus and system using the same. In particular, the invention relates to a photoelectric conversion apparatus, and an image pick-up apparatus and system such as a digital camera, a video camera, a copying machine, or a facsimile machine.
2. Related Background Art
An image sensor has been installed in many kinds of apparatuses such as a digital camera, a video camera, a copying machine, and a facsimile machine, where solid state image pick-up devices including photoelectric conversion devices are arranged in a one- or two-dimensional array. Examples of such solid state image pick-up devices include a CCD image pick-up device and an amplification solid state image pick-up device.
There is a growing tendency to increase the number of pixels in those image pick-up devices. As the area per pixel is reduced, the area allotted to the photodiode accordingly tends to be smaller. Thus, there arise a need to process a smaller quantity of signal charge and a need to lessen a leak current that may result in a noise component.
FIG. 4 shows a circuit configuration example of an amplification solid state image pick-up device. The amplification solid state image pick-up device includes at least in a unit pixel: a photodiode; and an amplifying transistor that amplifies light signals accumulated in the photodiode. The unit pixels are arranged in a two-dimensional array.
FIG. 5 is a plan view showing a pixel structure in a unit cell in a conventional amplification MOS sensor. In FIG. 5, reference numeral 2101 denotes a photodiode for photoelectric conversion; 2102, a reset transistor for resetting the photodiode 2101 and a floating diffusion (FD) region 2106; 2103, a transfer MOS transistor for transferring (reading out) signal charges in the photodiode 2101; 2104, a source follower amplifier for converting the transferred (read-out) charges into a voltage, with its gate electrode connected to the FD region 2106; and 2105, a row selection MOS transistor that connects an output of the source follower amplifier to a signal line.
In this layout, the FD region 2106 is constituted of an L-shaped diffusion layer in order to minimize its capacitance value CFD, in order to improve a charge-voltage conversion efficiency. Such a structure is disclosed in JP 2002-190586 A. Also, a depletion layer region 2208 is formed between the FD region 2106 constituted of an n+ layer and a p-type substrate. FIG. 6 is a plan view of a unit cell of a solid state image pick-up device disclosed in JP H10-150182 A. In the structure shown in FIG. 6, unlike FIG. 5, gate wirings 23 and 24 of a readout transistor are not discrete for each pixel and are not arranged close to a drain 25 of the readout transistor.
The transfer MOS transistor 2103 of the transistors in FIG. 5 is an NMOS transistor, and has a gate electrode formed of a material including N-type polycrystalline silicon.
FIG. 7 is a sectional view taken along the line 7—7 of FIG. 5. In FIG. 7, reference numeral 2201 denotes an N-type silicon substrate; 2202, a P-type well; 2203, a P+ type channel stop layer that is formed below a local-oxidation-of-silicon (LOCOS) oxide film 2204 in a self-aligned manner; 2205, an N+ type diffusion layer that constitutes part of the FD region 2106; 2206, a gate electrode that is formed of high-concentration N-type polysilicon or silicide thereof; and 2207, a gate insulating film of the transfer MOS transistor 2103.
Next, circuit operation is explained with reference to a circuit diagram of FIG. 8 and a timing chart of FIG. 9.
In operation, the circuit is shifted from a state where the reset MOS transistor 2102 is turned ON to a state where the transfer MOS transistor 2103 is turned ON for resetting the photodiode 2101 of FIG. 8. After that, the transfer MOS transistor 2103 is turned OFF to reset the photodiode 2101. The photodiode in the reset state is then put into a charge accumulating state. After the lapse of a certain accumulation period, the reset MOS transistor 2102 is turned OFF and the row selection MOS transistor 2105 is turned ON. Thus, the source follower amplifier 2104 is activated. In this state, the voltage value of a vertical output line 2108 at the time of resetting the FD region 2106 is input (written) to a noise readout storage capacitor (Ctn) 2107 by turning ON a transfer transistor 2109. Then, the transfer transistor 2109 is turned OFF. Note that the time chart of FD in FIG. 9 schematically shows a voltage value change of the floating diffusion (FD) region 2106.
Next, the transfer MOS transistor 2103 is turned ON again, thereby to transfer signal charges in the photo diode 2101 to the FD region 2106. With this transfer, a potential change corresponding to the transferred signal charges appears in the time chart of FD In this state, a voltage value of the vertical output line 2108 at the time of transferring the signal charges to the FD region 2106 is input (written) to a signal readout storage capacitor (Cts) 2110 by turning ON a transfer transistor 2111. Then, the transfer transistor 2111 is turned OFF.
After that, a differential amplifier, etc., (not shown) are used for generating a voltage corresponding to a difference between the output charge of the storage capacitor Cts and that of the storage capacitor Ctn. This makes it possible to eliminate noise generated at the reset time of the reset MOS transistor 2102 of the pixel or variation in threshold voltage of the source follower amplifier 2104.
Here, in a layout portion as shown in a region of FIG. 7 where the N+ type FD region 2205 and the P+ type channel stop layer 2203 are formed close to each other and, in addition, the N+ type poly-Si electrode overlies the P+ type channel stop layer 2203, a leak current is more likely to flow between the FD region and the substrate. If the leak current is generated in this portion, as indicated by the dotted line in the time chart of FD of FIG. 9, the voltage of the FD region changes. As a result, the voltage values input (written) to the storage capacitors Ctn and Cts are different from the original (correct) ones, leading to a deterioration in image quality.
Regarding JP H10-150182 A, this publication has no description about an influence that may be exerted on how the depletion layer spreads by a concentration of a semiconductor layer close to the drain 25 or a concentration of a semiconductor region just below the gate wirings 23, 24 but excluding a channel formation region, or a work function of a material for each gate wiring. In a structure like that of FIG. 6, when a difference in work function between the gate electrode and the semiconductor region just below the gate wirings 23, 24 but excluding the channel formation region, takes a positive value or zero, as explained below, even if the channel stop is disposed close to the FD region, a leak current will not increase. Accordingly, the use of a structure of the present invention provides not noticeable but substantial advantage at least rather than the prior art.